As semiconductor development continues to optimize the performance of advanced CMOS, it has become clear that new features are required beyond conventional scaling. For high-performance CMOS, and particularly CMOS on thin silicon-on-insulator (SOI) layers, a raised source/drain structure has been proposed to improve parasitic resistance. More recently, strained silicon has also been proposed for enhanced performance either as part of the crystal lattice in the channel, or alternatively, deformation of the silicon lattice in the channel by external stress techniques. A third method used in the prior art is to provide a very steep retrograde well structure that improves mobility and short channel performance.
One such technique is to provide a strained layer on the source and drain regions using SiGe. In order to enable significant strain on the channel, it is preferable to recess the silicon in the source/drain region and then grow a strained SiGe selective epi film in these recessed areas. One problem with this approach is that the recess of the source/drain silicon must be controlled and reproducible to obtain a manufacturable process. Traditionally, this recess was done using a wet etch or a dry plasma etch in a timed fashion. These methods suffer from the fact that the etch rate may vary from day to day and also the surface of the silicon being etched is variable and may have a variable induction time before etching begins. This leads to a poorly controlled recess that is not suitable for large-scale manufacturing.
In view of the above, a method is needed in which a recessed strained raised source/drain structure can be obtained wherein the recess of the source and drain silicon is controllable and reproducible thereby providing a manufacturable process.